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AD1870
REV. A
–
17
–
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
32
1
2
3
4
5
17
SOUT
OUTPUT
TAG
OUTPUT
20
21
22
1
2
3
INPUT
WCLK
OUTPUT
HI
HI
6
18
19
MSB
LEFT TAG
MSB
LSB
RIGHT TAG
MSB-14
LSB
PREVIOUS DATA
MSB-1 MSB-2 MSB-3
LEFT DATA
MSB-4
MSB-3 MSB-4
LSB
MSB-1 MSB-2
RIGHT DATA
LSB
MSB-1
LEFT DATA
MSB
MSB
LEFT TAG
MSB
RIGHT TAG
L
R
CK
INPUT
MSB
LSB
MSB
LSB
Figure 16. Serial Data Output Timing: Slave Mode, I
2
S-Justified, 32-Bit Frame Mode,
S/
M
= Hl, R
L
JUST = LO,
MSBDLY
= LO
BCLK OUTPUT (64 x
f
S
)
RDEDGE = LO
BCLK OUTPUT (64 x
f
S
)
RDEDGE = HI
CLKIN
INPUT
WCLK
OUTPUT
DATA AND TAG
OUTPUTS
t
DLYCKB
t
BPWL
t
BPWH
t
BPWL
t
BPWH
t
DLYBLR
t
DLYDT
t
DLYBWR
t
DLYBWF
L
R
CK
OUTPUT
XMIT
XMIT
XMIT
XMIT
Figure 17. Master Mode Clock Timing
WCLK
INPUT
DATA AND TAG
OUTPUTS
XMIT
t
BPWL
t
BPWH
t
BPWH
t
BPWL
t
DLYLRDT
MSB
MSB-1
t
DLYBDT
t
SETLRBS
BCLK INPUT
RDEDGE = LO
BCLK OUTPUT
RDEDGE = HI
L
R
CK
INPUT
t
SETWBS
SAMPLE
XMIT
SAMPLE
Figure 18. Slave Mode Clock Timing
CLKIN INPUT
RESET
INPUT
t
CPWH
t
CPWL
t
CLKIN
t
RPWL
Figure 19. CLKIN and
RESET
Timing
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相关PDF资料
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